Thermal resistance from the top to the bottom of the board through an array of vias under a component pad, for example an exposed pad of a regulator or power transistor. Includes the dielectric between the vias and the effect of filling the vias.
One via. Heat flows along the copper barrel and, if filled, through the fill: G = (kCu·Abarrel + kfill·Ahole) / L, Rvia = 1/G.
Array. N vias in parallel: Rvias = Rvia/N. The dielectric under the rest of the pad conducts in parallel: Rdiel = L/(kdiel·(Apad − N·Avia)). The total is the parallel combination, and the temperature drop is ΔT = P·Rtotal.
Limits. One-dimensional model through the board thickness. It does not include spreading resistance in the copper planes, the solder joint or the convection from the board surfaces. These usually dominate the overall junction-to-ambient resistance, so use the result to compare via layouts rather than as the full thermal path. Fill conductivities are typical values. Check your manufacturer's data.
As many as fit at the manufacturer's minimum pitch (often 1 to 1.2 mm with 0.3 mm holes). Returns diminish once the vias are no longer the largest resistance in the path.
Open vias in a soldered pad can draw solder away from the joint. Tenting, plugging or filling them, or using small holes, avoids it.
Width a trace needs for a current, or the current a trace can carry, with IPC-2152 and IPC-2221.
Current capacity, resistance, thermal resistance, capacitance and inductance of a plated via.
Current that melts a trace in a given time (Onderdonk), or how long a trace survives a fault current.
Impedance of an outer-layer trace over a plane, with solder mask or embedded, and width for a target impedance.
Impedance of an inner-layer trace between two planes, symmetric or offset, and width for a target.
Differential, odd, even and common-mode impedance of edge-coupled microstrip and stripline pairs.