Characteristic impedance of a trace on an outer layer over a reference plane, or the width needed for a target impedance such as 50 Ω. Optional solder mask or a covering prepreg layer (embedded microstrip). Also gives the effective dielectric constant, delay and inductance and capacitance per length.
Model. Hammerstad and Jensen's closed-form equations for the impedance of a microstrip in a homogeneous medium and its effective dielectric constant, valid for any width-to-height ratio with an error of about 0.2 % for zero thickness. Copper thickness is included through Wheeler's equivalent width correction (Δu depends on t/h and on εr).
Solder mask and embedded microstrip. A dielectric layer above the substrate raises the effective dielectric constant: εeff,coated = εeff + Δq · (εr,cover − 1), where Δq is the share of the field that the layer occupies (Wan and Hoorfar's filling factor for a three-layer microstrip). The impedance then scales as Z = Zuncoated · √(εeff / εeff,coated). The mask is modelled as a flat layer of the given thickness.
Derived values. Delay per length = √εeff / c; L = Z·√εeff / c; C = √εeff / (Z·c). Width synthesis solves the same equations numerically.
Accuracy. Compared with a 2D field solver, within about 1–2 % for 1 oz copper on dielectrics of 0.2 mm and thicker. Expect up to about 4 % when the copper is thick compared with the dielectric (t/h > 0.3). The model is static and does not include frequency dispersion, which raises the impedance slightly at several GHz.
Use the value your manufacturer gives for the specific core or prepreg at your frequency, usually between 3.8 and 4.6. Many fabricators publish their stackups with these values.
Yes. A typical liquid solder mask lowers a 50 Ω microstrip by roughly 1 to 3 Ω, depending on its thickness and on the trace geometry.
Impedance of an inner-layer trace between two planes, symmetric or offset, and width for a target.
Differential, odd, even and common-mode impedance of edge-coupled microstrip and stripline pairs.
Impedance of a coplanar waveguide, with or without a ground plane underneath (grounded CPW).
Width a trace needs for a current, or the current a trace can carry, with IPC-2152 and IPC-2221.
Current capacity, resistance, thermal resistance, capacitance and inductance of a plated via.
Thermal resistance of an array of vias under a pad, with fill options, and the temperature drop through the board.