Find the minimum trace width for a current, or the maximum current of an existing trace, for a given copper weight and temperature rise. Results from IPC-2152 and the older IPC-2221 are shown side by side, with the trace resistance, voltage drop and power loss.
IPC-2152. The standard publishes charts, not equations. The calculator uses the curve fit of those charts by Brooks and Adam: ΔT = K · Ia · Wb · Thc, with width W and thickness Th in mils. External layers use K = 215.3, a = 2.0, b = −1.15, c = −1.0. Internal layers use a separate set for each copper weight (½ to 3 oz). Solving for W or I gives the minimum width or the maximum current.
IPC-2221. The older chart is the familiar I = k · ΔT0.44 · A0.725, with A the cross-section in mil², k = 0.048 for external and k = 0.024 for internal conductors.
Resistance. R = ρ(T) · L / (W · t), with ρ(20 °C) = 1.724×10−8 Ω·m and a temperature coefficient of 0.00393 /K, evaluated at ambient + temperature rise.
Which one to use. IPC-2152 replaced IPC-2221 for current capacity. Its baseline is conservative: a single trace on a board with no nearby copper planes, in still air. A plane under the trace, a thicker board or forced air reduce the real temperature rise considerably. At high currents IPC-2152 asks for wider external traces than IPC-2221.
IPC-2152 is based on newer measurements of a single trace far from any copper plane. It is deliberately conservative. With a ground or power plane close to the trace the temperature rise is lower than the chart predicts.
10 °C is a common conservative choice. 20 to 30 °C is usual for power traces, provided the board, components and solder mask tolerate the resulting temperature.
Current capacity, resistance, thermal resistance, capacitance and inductance of a plated via.
Thermal resistance of an array of vias under a pad, with fill options, and the temperature drop through the board.
Current that melts a trace in a given time (Onderdonk), or how long a trace survives a fault current.
Impedance of an outer-layer trace over a plane, with solder mask or embedded, and width for a target impedance.
Impedance of an inner-layer trace between two planes, symmetric or offset, and width for a target.
Differential, odd, even and common-mode impedance of edge-coupled microstrip and stripline pairs.