Electrical and thermal properties of a plated through via: how much current it can carry, its resistance and thermal resistance, and the parasitic capacitance and inductance that matter for fast signals.
Current capacity. The plated barrel is treated as a conductor with cross-section A = π/4 · ((d + 2tp)² − d²) and the IPC-2221 external-conductor relation I = 0.048 · ΔT0.44 · A0.725 (A in mil²). This is the usual approach in via calculators. A via is short and sits between pads, so in practice it runs cooler than a trace of the same section.
Resistance and thermal resistance. R = ρ(T)·L/A and Rth = L/(kCu·A), with kCu = 385 W/m·K.
Parasitics. Howard Johnson's approximations (dimensions in inches): C = 1.41·εr·T·D1/(D2−D1) pF, with D1 the pad and D2 the antipad diameter, and L = 5.08·h·[ln(4h/d) + 1] nH. Via impedance = √(L/C). The rise-time degradation in a line of impedance Z0 is 2.2·C·Z0/2.
Accuracy. The parasitic values are first-order estimates, useful for comparing via options. Stubs and the return path through nearby vias are not included and need a 3D solver.
A 0.3 mm via with 25 µm plating in a 1.6 mm board carries roughly 1.5 to 2 A for a 10 °C rise by this method. Use several vias in parallel for power connections.
Yes. The capacitance grows as the gap between pad and plane shrinks, which lowers the via impedance. Removing unused inner pads also reduces it.
Width a trace needs for a current, or the current a trace can carry, with IPC-2152 and IPC-2221.
Thermal resistance of an array of vias under a pad, with fill options, and the temperature drop through the board.
Current that melts a trace in a given time (Onderdonk), or how long a trace survives a fault current.
Impedance of an outer-layer trace over a plane, with solder mask or embedded, and width for a target impedance.
Impedance of an inner-layer trace between two planes, symmetric or offset, and width for a target.
Differential, odd, even and common-mode impedance of edge-coupled microstrip and stripline pairs.