Characteristic impedance of a trace with ground copper on both sides, with or without a ground plane underneath. Grounded CPW is common for RF traces to antennas and connectors.
Model. Conformal mapping (Wen; Ghione and Naldi). With k1 = w/(w+2s): for CPW without a bottom ground, εeff = 1 + (εr−1)/2 · [K(k2)/K(k2′)] / [K(k1)/K(k1′)] with k2 = sinh(πw/4h)/sinh(π(w+2s)/4h), and Z0 = 30π/√εeff · K(k1′)/K(k1).
For grounded CPW, k3 = tanh(πw/4h)/tanh(π(w+2s)/4h) and Z0 = 60π/√εeff / [K(k1)/K(k1′) + K(k3)/K(k3′)].
Copper thickness. Gupta's correction widens the strip and narrows the gap by Δ = 1.25t/π · (1 + ln(4πw/t)) and lowers the effective dielectric constant, because more of the field sits in the air-filled gaps.
Accuracy. About 3 % against a 2D field solver for 1 oz copper. The side grounds are assumed wide, and grounded CPW needs a row of stitching vias along both edges.
When the trace has to be narrow on a thick board, or when you want the field tightly confined and well isolated, for example from an RF chip to an antenna connector.
A common rule is less than a tenth of a wavelength at the highest frequency of interest, and close to the gap edge.
Impedance of an outer-layer trace over a plane, with solder mask or embedded, and width for a target impedance.
Impedance of an inner-layer trace between two planes, symmetric or offset, and width for a target.
Differential, odd, even and common-mode impedance of edge-coupled microstrip and stripline pairs.
Width a trace needs for a current, or the current a trace can carry, with IPC-2152 and IPC-2221.
Current capacity, resistance, thermal resistance, capacitance and inductance of a plated via.
Thermal resistance of an array of vias under a pad, with fill options, and the temperature drop through the board.